T1C — short for Tier 1 Chip — is an open-source AI accelerator architecture built under ADDX Entp. The architecture, instruction-set specification, fabrication planning and contribution paths all sit in a public repository. It is a design and research project, not a shipped product — and that is exactly why it is being shared now.
We design it. World builds it.
T1C asks one question: can an AI accelerator be designed openly enough that other engineers can study it and extend it, instead of treating the chip as a sealed black box?
For most AI workloads, raw arithmetic is only part of the cost. Moving weights, activations and KV-cache data between memory and compute can dominate the practical design far more than the multiply-accumulate operations themselves — the classic Von Neumann bottleneck, which gets worse as models grow.
T1C's answer is digital in-memory computing (D-IMC): pushing more of the computation physically closer to where the data already sits, so less of it has to move at all.
D-IMC conceptsMIM partitions a single chip so that up to four isolated tenants can run separate workloads on the same piece of silicon without stepping on each other. For shared AI infrastructure, that could make capacity far more predictable and affordable.
Isolation is a much bigger problem than dividing memory into regions. It requires explicit resource accounting, quality-of-service assumptions, scheduling behaviour, error handling, and analysis of possible side channels. T1C presents MIM as an architectural direction worth stress-testing — not a finished security guarantee.
Multi-tenancy modelT1C is explicitly not positioned as a faster chip than an H100. Its case rests on a different set of trade-offs entirely — openness, cost, and buildability.
Nine architectural operations — matrix multiply, accumulation, KV-cache read/write, DMA, softmax, RMS norm, partition config. Register classes and encoding are published, not hidden.
Not "coming soon". Free research shuttles through IHP Germany at 130nm, plus GlobalFoundries, Efabless and Tiny Tapeout routes that are available today.
Published figures are architectural projections, clearly labelled as such. No fabricated ranking claims, no artificial traffic, no borrowed benchmarks.
Free to use, modify, fabricate and sell. Attribution is appreciated but not legally required. The whole project — docs, ISA, planning — lives in one public repository.
T1C has not been fabricated. Every figure below is an architectural projection from the repository — stated plainly, because a number you cannot verify is not a number worth shipping.
| System | LLaMA 7B speed | Max model | Cost | Open source |
|---|---|---|---|---|
| T1C — 1 blade | 12–20 tok/s | ~64B (INT4) | $280–$650 | MIT |
| T1C — 8 blades | 96–160 tok/s | ~512B (INT4) | $2,240–$5,200 | MIT |
| NVIDIA RTX 4090 | 80–100 tok/s | ~24B (FP16) | $1,500 | No |
| NVIDIA H100 | 1000+ tok/s | Unlimited | $30,000 | No |
T1C is not faster than an H100 and does not claim to be. The pitch is openness, DIY buildability, hardware tenant isolation at a low price point, and an Indian-designed alternative to a market dominated by closed, expensive silicon.
| The problem today | T1C's approach |
|---|---|
| An NVIDIA H100 costs around $30,000 | A T1C blade is estimated at $280–$650 |
| Closed source — you cannot modify it | Fully open source, MIT licensed |
| Needs a specialised cleanroom | Fabricatable through community shuttle runs |
| Von Neumann bottleneck | D-IMC — compute happens inside memory |
| No affordable hardware multi-tenancy | MIM — four isolated tenants per chip |
The repository lays out concrete, presently-available fabrication paths rather than a vague "coming soon". The recommended starting point is IHP Germany — a free research shuttle route for open-source projects, which removes the single biggest cost barrier to a first physical test chip.
| Method | Node | Cost | Availability |
|---|---|---|---|
| IHP Germany (research) | 130nm | Free | Available now |
| GlobalFoundries 65LP MPW | 65nm | $15–40 / chip | Available now |
| Efabless + SkyWater | 130nm | $100–300 / slot | Available now |
| Tiny Tapeout | 130nm | ~$100 / slot | Available now |
T1C has not been taped out, fabricated, or brought to silicon. There are no measured silicon results, no validated production-cost figures, and no finished commercial benchmarks to point to yet.
Contribution paths are split by discipline, with named unclaimed items. Full details live in the repository's CONTRIBUTING.md.
Verilog modules for the MAC array, KV-cache controller, DMA engine, MIM MMU and voltage monitor — plus the KiCad blade PCB layout.
A llama.cpp backend, a Verilator simulation model, a Python assembler, a Linux kernel driver, and an ONNX Runtime provider.
Documentation improvements, translations, blog posts and tutorials, testing and bug reports — and honest critique of the weakest assumptions.
From India — for the world. The architecture documents and ISA specification go well beyond what is summarised here, and the repository is where the real discussion happens.