The repository is structured so a reader can follow the project from high-level architecture all the way to the components that still need engineering work.
T1C — short for Tier 1 Chip — is an open-source AI accelerator architecture. It is released as a public engineering project: architecture, instruction-set specification, fabrication planning and contribution paths all sit in a public repository for anyone to inspect, question, or build on.
The project is deliberately blunt about where it stands. It is a design and research project, not a shipped product.
We design it. World builds it.
Four ideas work together: digital in-memory computing, a memory-isolated multi-tenancy model, an open instruction-set specification, and a hardware/software structure aimed specifically at large language model inference.
The tree is organised so each discipline knows where its work belongs:
| Directory | Contents |
|---|---|
docs/ | System architecture, blade-level design, D-IMC concepts |
isa/ | Instruction-set spec, register classes, encoding, example assembly |
rtl/ | Verilog hardware modules — largely unclaimed |
pcb/ | KiCad blade board design |
sim/ | Verilator simulation models |
software/ | llama.cpp backend, kernel driver, ONNX Runtime provider |
tools/ | Python assembler and supporting tooling |
T1C ships with a documented ISA — currently nine architectural operations: matrix multiplication, accumulation, KV-cache reads and writes, DMA transfers, softmax, RMS normalisation, and multi-tenant partition configuration.
The isa/ directory includes register classes, instruction encoding, memory mapping, and a worked example assembly program.
Whether nine operations is the right instruction boundary is treated as an open question. A real implementation may well need changes after modelling, compiler work, workload analysis, or RTL validation.
For most AI workloads, raw arithmetic is only part of the cost. Moving weights, activations, intermediate values and KV-cache data between memory and compute units can dominate the practical system design far more than the multiply-accumulate operations themselves — the classic Von Neumann bottleneck, which worsens as models grow.
D-IMC pushes more of the computation physically closer to where the data already lives, so less of it has to move. This is not free of new problems, and the project says so rather than hiding it behind a product claim: putting compute inside memory raises questions around mapping, numerical precision, calibration, SRAM organisation, and verification. Those open questions are left visible in the repository on purpose.
MIM partitions a single chip so up to four isolated tenants can run separate workloads on the same silicon without stepping on each other. Isolation requires more than dividing memory into regions:
T1C presents MIM as an architectural direction worth examining and stress-testing — not as a finished security guarantee.
Compressing or more efficiently placing the KV-cache could meaningfully improve effective capacity for decoder-style inference workloads — but only if the benefit holds up once you account for accuracy impact, access patterns, decode latency, decompression overhead, and how differently various model families behave.
These are exactly the kind of claims that deserve testing against a small reference model before they get frozen into a hardware requirement.
T1C does not exist in a vacuum. NVIDIA remains dominant at roughly 80–90% of the discrete GPU market, with Blackwell B200 delivering around 2.5 petaflops of FP8 tensor performance. Google's TPU v7 "Ironwood", AWS Trainium3, and AMD's MI300X/MI350X continue to close the gap on raw specs.
The most interesting shift is inference-first architectures — Groq's LPU treats token generation as a scheduling problem, and Cerebras goes further with the wafer-scale WSE-3. All of these are, in their own ways, closed and capital-intensive.
That is the specific gap T1C aims at — not competing on raw tokens-per-second, but asking what an AI accelerator looks like when the full architecture, ISA and fabrication path are public, and a working blade costs a few hundred dollars instead of tens of thousands.
Contribution paths are split by discipline, with specific unclaimed items rather than a generic "help wanted":
| Discipline | Unclaimed work |
|---|---|
| Hardware | rtl/mac_array.v · rtl/kv_cache.v · rtl/dma_engine.v · rtl/mim_mmu.v · rtl/voltage_monitor.v · pcb/blade_v1.kicad_pcb |
| Software | software/llama_cpp_backend/ · sim/maau_verilator/ · tools/assembler/ · software/kernel_driver/ · software/onnx_provider/ |
| Anyone | Documentation, translations, blog posts and tutorials, testing and bug reports |
Full details are in the repository's CONTRIBUTING.md. The project is MIT licensed — free to use, modify, fabricate and sell, with attribution appreciated but not legally required.
T1C has not been taped out, fabricated, or brought to silicon. There are no measured silicon results, no validated production-cost figures, and no finished commercial benchmarks. Physical implementation, RTL validation, reproducible software modelling, tape-out, silicon testing and hardware benchmarking are all future milestones — not implied achievements.
The author is actively looking for critique on: which part should be modelled first, which assumptions are weakest, which workloads would expose the architecture's limitations, and what a credible minimum demonstration should look like before any tape-out discussion begins.