Openness only matters if the design can actually be built. These are the concrete, presently-available fabrication paths — not a vague "coming soon".
A free research shuttle route for open-source projects. Removes the single biggest cost barrier to a first physical test chip — the recommended starting point.
Multi-project wafer run at a smaller node. Cheapest per-die option once the design has been validated on a first shuttle.
Open-access slot on the SkyWater 130nm process through Efabless, with a mature open toolchain around it.
| Method | Node | Cost | Availability |
|---|---|---|---|
| IHP Germany (research) | 130nm | Free | Available now |
| GlobalFoundries 65LP MPW | 65nm | $15–40 / chip | Available now |
| Efabless + SkyWater | 130nm | $100–300 / slot | Available now |
| Tiny Tapeout | 130nm | ~$100 / slot | Available now |
Costs are the figures published in the T1C repository. They are planning estimates for shuttle and MPW access, not validated production-cost figures — T1C has not been fabricated yet.
The comparison that matters is not tokens per second. It is whether an independent engineer or a university lab can afford to put the design on real silicon at all.
| System | LLaMA 7B speed | Max model | Cost | Open source |
|---|---|---|---|---|
| T1C — 1 blade | 12–20 tok/s | ~64B (INT4) | $280–$650 | MIT |
| T1C — 8 blades | 96–160 tok/s | ~512B (INT4) | $2,240–$5,200 | MIT |
| NVIDIA RTX 4090 | 80–100 tok/s | ~24B (FP16) | $1,500 | No |
| NVIDIA H100 | 1000+ tok/s | Unlimited | $30,000 | No |
Figures are architectural projections from the T1C repository, not measured silicon benchmarks. T1C is not faster than an H100 and does not claim to be.
That is why the project is open now rather than later — while the architecture is still cheap to change.